FIG. 1 depicts an example of a chip set 100 that includes some general-purpose read-only memory (ROM) 110 connected to a general-purpose FPGA 120. FPGA 120 conventionally includes an array 130 that can be configured to implement custom functional circuitry 140. Array 130 typically includes a collection of configurable logic blocks (CLBs), memory blocks, and input/output blocks (IOBs) that can be interconnected using programmable interconnect resources.
A vendor may use a chip set similar to chip set 100 to supply any number of different circuit designs while stocking only a single general-purpose FPGA and some general-purpose memory. The vendor supplies a customer with a custom version of chip set 100 by simply programming ROM 110 with the configuration data required to implement the customer's desired functions.
Configuration data are typically downloaded into an FPGA (or other types of programmable logic devices) as a series of bits known as a configuration bitstream. Anyone having access to the configuration bitstream for a particular design can easily copy the design. In the foregoing example in which a vendor sells a custom circuit as a set of configuration data combined with a general-purpose FPGA, an unscrupulous customer could easily copy the configuration data and use it to program any number of additional FPGAs. Designs may also be stolen by reverse engineering the design from the configuration bitstream and then adapting the design for another FPGA or even a different circuit technology. Naturally, developers of custom configuration data for use in programmable chip sets are concerned for the security of their designs.
Some customers develop their own circuit designs and implement them on FPGAs. Designing complex circuits from basic logic gates, or “primitive cells,” can be very time consuming. More complex functions called macros, or “cores,” are therefore developed to represent more complex logic functions. These cores can then be used as building blocks for assembling still more complex circuit designs.
A number of core developers design and market cores for FPGAs and other types of programmable logic devices (PLDs). Customers purchase these cores and use them to program PLDs to achieve desired functions. For example, a collection of cores for implementing standard bus interfaces and signal-processing functions is available from Xilinx, Inc., of San Jose, Calif., under the name LogiCORE™. As with the configuration data in the example of FIG. 1, PLD cores and circuit designs that employ them are easily stolen. Core developers are therefore concerned for the security of their cores.
Some PLD manufactures address the security concerns of PLD customers and core developers by supporting bitstream encryption schemes. PLDs can include hard-wired or programmably instantiated decryptors that access decryption keys stored on the PLD in non-volatile memory. Proprietary bitstreams can then be encrypted for storage and delivery.
When PLDs support decryption circuits programmably instantiated on an FPGA, a clever thief can engineer a “Trojan Horse” design that, when instantiated, simply reads the decryption key and presents the key on an output pin of the FPGA. Steps should therefore be taken to prevent such designs from jeopardizing proprietary keys and the data they are intended to protect.